Informatics Publishing Limited

S. Preetha ¹, R. Raghavi ¹, Y. Sri Lakshmi ¹, C. T. Kavitha ¹

Affiliations
1 Dept of Electronics and Communication, Jerusalem College of Engineering, Velachery, Chennai 600100, IN

Abstract

The purpose of this paper is to build vehicle number plate recognition for intelligent transport system. Number plate localization and recognition is an image processing technology used to identify vehicle by the number plates. that follows the RTO standards. This system is based on image capturing of the particular vehicle whose number plate is to be localized. Then segment the number plate and recognize each character of the number plate from the image by comparing it with standard RTO template emphasized by the government. .Thus the number plate of the vehicle is obtained. This very special technique finds use in social applications like tracking out the vehicle that violates the traffic rules on roads, violating the parking rules and checking at the toll-gates.

Keywords

Number Plate, Localization, Recognition, Segmentation, Template, RTO Standards.

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V. Rama Raju ¹, Y. Sri Lakshmi ², E. Brahma Reddy ³

Affiliations
1 ECE & CSE Dept., SSN College of Engg. & Technology, Ongole, Prakasham-523002, AP, IN
2 ECE Dept., SSN College of Engg. & Technology, Ongole, Prakasham-523002, AP, IN
3 CSE Dept., SSN College of Engg. & Technology, Ongole, Prakasham-523002, AP, IN

Abstract

Leakage (or static power consumption) and Glitches are two of the major problems faced by the semiconductor nanometer technologies. This project develops new power minimization methods for digital CMOS circuits considering two components of power, namely, the leakage power and the glitch power are minimized while the overall circuit delay is controlled. Arithmetic circuits like adders and multipliers are essential components in the design of circuits in ASIC. To design low power high sped arithmetic circuits a combination of techniques at four levels is required. They are Algorithm, architecture, circuit and system levels. With the continuous increase of the density and performance of integrated circuits due to the scaling down of the CMOS technology, reducing power dissipation becomes a serious problem that every circuit designer has to face. Digital multiplication is not the most fundamentally complex operation, but is the most extensively used operation. Innumerable schemes have been proposed for realization of the operation. Various multiplier architectures are compared in terms of dissipated energy, propagation delay, energy-delay product (EDP), and area occupation, in view of low-power low-voltage signal processing for lowfrequency applications. A novel practical approach has been set up to investigate the mechanisms of glitch generation and propagation. It is found that spurious activity is a major cause of energy dissipation in multipliers. Measurements point out that, because of its shorter full-adder chains, the TG-multiplier dissipates less energy than other traditional array multipliers. By combining transmission gates with static CMOS in TG-multiplier architecture, a new approach is proposed to improve the energy-efficiency for low-power architectures. The project consists in suppressing glitches via resistance-capacitance low-pass filtering, while preserving unaltered driving capabilities. The reduced number of Vddto- ground paths also contributes to a significant decrease of static consumption.

Keywords

Multipliers, TG Full Adders, 10 Transistor Adders, Low Power Design.

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